1. Field of the Invention
The present invention relates to the field of memories and more particularly to a technique of performing post erase repair on flash memory.
2. Description of the Related Art
One type of non-volatile electrically erasable and electrically programmable read only semiconductor memory is commonly referred to as a flash memory. Once programmed, the flash memory retains the program data until the memory is erased. In a typical flash memory erase routine, a block of memory is erased instead of individual cells. A variety of flash memory devices are known in the art, but generally, a flash cell is comprised of a metal-oxide-semiconductor (MOS) transistor which includes an isolated or floating gate that is programmed, typically by electron injection from the channel.
In one typical configuration, a flash cell is programmed by applying a high voltage (such as 12 volts) on the control gate, 0 volts on the source and an intermediate voltage such as 6 volts on the drain. A channel-hot-electron injection causes the isolated or floating gate to be negatively charged. The charged floating gate causes the threshold voltage (Vt) of the device to increase. Thus, a programmed cell requires a higher threshold voltage to turn the transistor on as compared to an erased cell. In a read operation, generally, the source is grounded and a read voltage, such as 5 volts, is applied to the control gate and the output is determined at the drain. The amount of the read current at the drain determines if the device is programmed or not programmed.
In order to erase the programmed cell, the drain is made to float while a voltage is impressed across the source and the control gate, such as 12 volts on the source with a grounded control gate or 5 volts on the source with a negative voltage (such as xe2x88x928 V) on the control gate. When the cell is being erased, charges are removed from the floating gate to the source terminal so that the threshold voltage of the device is reduced. Accordingly, the erase threshold voltage, Vte, is less than the program threshold voltage Vtp. Therefore, a programmed cell has a charged floating gate which requires a much higher threshold voltage to turn on the cell, while an erased cell has charges removed from the floating gate so that a lower threshold voltage will turn on the cell.
As noted above, flash memories are generally erased in chunks of memory cells commonly referred to as arrays or blocks. Thus, a block erase of a memory device results in all of the memory cells of that block undergoing an erase procedure. It is appreciated that multiple blocks generally reside within a flash memory device.
One common problem with the block erase is that some of the memory cells may be over erased. An over erased condition occurs when the threshold voltage of the device is near or below zero volts so that the cell will leak current (have a leakage current in the drain) when the cell is erased. Accordingly, after a block erase it is possible and typically probable that one or more cells will erase into this over erased condition. In order to repair the over erased cells, a typically known practice is to soft program the cells in a sequence so that the threshold voltage of the over erased cells are increased to an acceptable level where the leakage is minimized or removed.
A well known prior art practice utilizes a routine to soft program all of the cells on a given bit line so that the threshold voltage level of the cells are increased. In this technique, an erase verification test is performed on each bit line and when a current exceeds a preselected reference value the bit line is noted to have one or more cells in the over erased condition. In this instance, the cells on the bit line are programmed through a sequence of steps in which the programming voltage is increased at predefined steps, until all of the cells of the bit line pass the current test or until the maximum repair programming voltage is reached at which point failure of the erasing program is noted.
One problem with this technique resides in the manner the verification of each cell is performed after a block erase procedure. Each cell on the bit line is verified to determine if it is properly erased. When a particular cell is selected, its bit line is checked to ensure that the cell is not in the over erased condition. Generally, it is preferable to program the cells such that each cell is at a minimum desired threshold voltage for proper operation of the cell. A problem with this technique is the difficulty in determining if the verified cell is operating below the desired threshold voltage or if one of the other deselected cells on the same bit line has excessive leakage current due to an over erased condition (such as having a negative threshold voltage) if the bit line indicates excessive current.
Therefore, monitoring the bit line to perform the over erase repair of memory cells utilizing this known technique requires a considerable number of looping through the array in order to blindly program each of the cells on the bit line until the current is below the accepted limit. When numerous cells are on a given column (such as in excess of 500 cells), significant programming time is required to sequence through the repair algorithm to repair cells on a given bit line.
What is needed is an improved technique to enhance the repair and verification of erased memory cells.